The present invention relates to a method and apparatus for charged particle beam exposure, and more particularly to a method and apparatus for drawing various patterns on a semiconductor wafer with a charged particle beam in the manufacture of semiconductor integrated circuits, for example.
It has been proposed, in a view of enhancement in the integration density of semiconductor integrated circuits, to use a charged particle beam such as an electron beam for drawing required circuit patterns on a semiconductor wafer, instead of using a conventional optical exposure technique. Since the patterns exposed through electron beam deflection include deflection distortions, it has been conventional to correct pattern data to be applied to the electron beam deflector.
In the manufacture of semiconductor integrated circuits the formation of each circuit pattern on the semiconductor wafer calls for a series of steps such as drawing of the pattern on the wafer, development of the exposed pattern, diffusion of an impurity into the wafer, etc.; namely, the fabrication of the semiconductor integrated circuits includes a plurality of pattern drawing steps. Some of these fabrication steps involve heating of the semiconductor wafer, which often leads to warping or deformation of the wafer by heat. If patterns as originally designed were exposed on such a warped or deformed semiconductor wafer even with an electron beam compensated for deflection distortion, their lines would become thin or close together, or pattern misalignment would occur between successive steps, making it impossible to obtain an intended semiconductor integrated circuit. This constitutes a serious obstacle to the fabrication of high density integrated circuits, in particular.
Fujinami et al discloses possibility of high precision pattern exposure through compensation for pattern distortions resulted from the deflection distortions and wafer warping in the literature entitled "PRECISION REGISTRATION METHOD FOR 0.5 .mu.m ELECTRON BEAM LITHOGRAPHY", IEDM 81, IEEE 1981, pp. 566-569. According to Fujinami et al, however, a set of correction coefficients are determined for each block which includes a plurality of chip areas, it is not possible to determine correction coefficients for smaller regions in each chip area.
As a solution to this problem, the following improvement has been proposed for the charged particle beam exposure process.
For example, assuming that 50 chip areas 10 are present on the top surface of a semiconductor wafer 11 as shown in FIG. 1, block marks 102A, 102B, 102C and 102D for defining the position of each chip area 10 are formed at four corners thereof by forming grooves in the wafer surface. Further, wafer marks 120-1 and 120-2 are similarly provided for indicating the reference position of the semiconductor wafer 11. The drawing of a pattern on the semiconductor wafer 11 starts with the detection of the block marks 102A throgh 102D of the chip area 10 where to expose the pattern, thereby checking alignment errors of the four block marks of the chip area which are resulted from the aforementioned warping or deformation of the semiconductor wafer 11. Then distortion correction coefficients are computed from the detected values of the shifts and design data of the pattern are corrected based on the coefficients, after which a corrected pattern is drawn in the desired chip area 10. With this method, an appreciably high density semiconductor integrated circuit could be produced with high precision even if the semiconductor wafer 11 has been warped or deformed through heating or cooling in each fabrication step.
In such a conventional method, however, since the correction coefficients for each chip area 10 are computed based upon only the four block marks 102A to 102D at the corners of the chip area, it is difficult or almost impossible to correct the pattern with sufficiently high precision throughout the chip area when each chip area 10 is large, in particular, when a high integration density is needed. Incidentally, the block marks cannot be provided inside the chip area since they would hinder the formation of circuits.
Each array of the chip areas 10 in the row direction will hereinafter be referred to as a unit area 104. Each chip area 10 is fictitiously divided into a plurality of smaller areas, four in the illustrated example, along the column direction and an array of such smaller areas in the row direction, as indicated by hatching in FIG. 1, will be called a unit belt 200. The charged particle beam exposure (hereinafter referred to as electron beam exposure because an electron beam is employed in general) for pattern drawing is usually carried out by directing an electron beam to a desired position in a relatively wide main deflection field through main deflection scanning control and deflecting the electron beam around the abovesaid position in a narrow sub-deflection field through sub-deflection scanning control. Let it be assumed that each chip area 10 measures 10 by 10 mm, the main deflection field 2.5 by 2.5 mm, and the sub-deflection field 80 by 80 .mu.m. In this example, the main deflection field is a square field each side of which is equal to the width of the unit belt 200. Since the designed position data of the block marks 102A through 102D are preknown, a stage carrying the semiconductor wafer 11 is moved so that one of the block marks defining one unit area 104 is supposedly positioned at the center of the main deflection field, which is followed by the sub-deflection scanning with the electron beam, and then the reflected beam is detected, thereby sensing the actual position of the block mark. Likewise, the actual positions of all the other block marks defining the unit area 104 are detected. Then correction coefficients for each chip area 10 in the unit area 104 are computed from the actual block mark positions detected for the chip area and an operation for correcting pattern data to be drawn in the chip area is performed, using the correction coefficients. After this, the main deflection field is brought to one end of one unit belt 200 in the unit area 104 and pattern data for drawing at that position (corrected according to the correction coefficients) is provided for the main and sub-deflection of the electron beam, which is followed by exposure of the semiconductor wafer (deposited over its surface with a photosensitive material layer, in practice) with the electron beam while moving the stage along the unit belt 200. This pattern drawing is carried out for each unit belt.
As will be seen from the above, according to the prior art method, the stage must be moved twice for the detection of the block marks and for the pattern drawing on the semiconductor wafer, so this takes much time as a whole; in some cases, the time for moving the stage acounts for approximately 40% of the total length of time for pattern drawing on the wafer.
As a solution to this problem, it has been proposed in, for instance, Japanese Patent Application Laid Open No. 67627/84, to perform the pattern drawing at the same time as the detection of the block marks. According to this method, the main deflection field is made a little larger than each chip area 10, which is divided into four exposure areas 101A, 101B, 101C, and 101D along the direction of extension of the unit area 104, as depicted in FIG. 2, and block marks 103A, 103B, 103C, . . . are formed on the semiconductor wafer 11 respectively corresponding to four corners of each of the exposing areas 101A to 101D. The stage is moved in the direction indicated by an arrow 105 so that the unit area 104 passes through the main deflection field 106. In this case, when the exposing area 101A enters the main deflection field 106, the positions of the block marks 103A to 103D are detected, the successive positions of deflection of the electron beam are corrected in accordance with the positions of the detected block marks, and patterns 107 and 108 are exposed in the area 101A as the unit area 104 travels. Upon completion of drawing the patterns 107 and 108 in the area 101A, the block marks 103E and 103F of the next exposing area 101B are detected, the successive positions of deflection of the electron beam are corrected on the basis of the detected positions of the newly detected block marks 103E and 103F and the previously detected positions of the block marks 103C and 103D, and then a pattern 109 is exposed in the area 101B.
The time for drawing required patterns on the semiconductor wafer can be reduced by drawing the patterns 107, 108, 109 . . . in the divided areas 101A, 101B, 101C, . . . while continuously feeding the unit belt 104, as described above. This permits the exposure of a number of wafers in a short time.
According to the above electron beam exposure method, however, the main deflection field 106 of the electron beam is selected slightly larger than the chip area 10. With such a large area of the main deflection field 106 of the electron beam, there will develop a deflection distortion or large aberration, impairing the drawing accuracy. Especially when the chip area 10 is large or when the integration density is desired to be increased, the deflection distortion and large aberration of the electron beam constitute an obstacle to the enhancement of the integration density. Moreover, when the chip areas 10 differ in size, it is necessary to change the main deflection field each time, accordingly.